Instruction Set

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The NIMJAR processor contains design features from both RISC and CISC architectures. The instruction set has support for variable length instructions of one or two words. A CISC approach is taken for implementation of a full descending stack and for subroutine call and return. The instruction set provides support for these through the { PUSH}, { POP}, { CALL} and { RETURN} instructions.

A RISC approach is taken for memory access, as direct memory access is possible through the { LOAD} and { STORE} instructions. Access to registers also uses a RISC approach, allowing all instructions to operate on any register.

Three addressing modes are supported by the instruction set; Register-register, register-short immediate and register-immediate. The addressing mode is defined by the arguments given by an instruction.

Register-register mode operates on a number of registers and are a single word instruction.

Register-short immediate mode operates on a register and a short (5- or 11-bit) immediate value contained within the instruction. These are single word instructions.

Register-immediate mode operates on a register and a 16-bit immediate value which is stored in the next memory location after the instruction. These are two word instructions.

Kmap.png

Instructions

ADD instruction

ADD

Mnemonic:

ADD

Description:

This instruction performs an arithmetic addition of a register, R[s], with another register, R[t] or an immediate value (either 5 or 16 bits). The result of the addition is stored in a register, R[d].

Register-register Mode:

Assembler Syntax:

ADD d, s, t

Opcode:

00101

Format:
Type1 0.png
Operation:

d ← s + t
N ← d[15]
Z ← if (d == 0) 1; else 0
C ← (s[15] & t[15]) | (!d[15] & (s[15] | t[15]))
V ← (s[15] & t[15] & !d[15]) | (!s[15] & !t[15] & d[15])


Register-immediate Mode:

Assembler Syntax:

ADD d, s, simm5

Opcode:

01101

Format:
Type2.png
Operation:

d ← s + simm5
N ← d[15]
Z ← if (d == 0) 1; else 0
C ← (s[15] & simm5[15]) | (!d[15] & (s[15] | simm5[15]))
V ← (s[15] & simm5[15] & !d[15]) | (!s[15] & !simm5[15] & d[15])


Register-long immediate Mode:

Assembler Syntax:

ADD d, s, simm16

Opcode:

00101

Format:
Type1 2.png
Operation:

d ← s + simm16
N ← d[15]
Z ← if (d == 0) 1; else 0
C ← (s[15] & simm16[15]) | (!d[15] & (s[15] | simm16[15]))
V ← (s[15] & simm16[15] & !d[15]) | (!s[15] & !simm16[15] & d[15])

SUB instruction

SUB

Mnemonic:

SUB

Description:

This instruction performs an arithmetic subtraction of a register, R[t], from another register, R[s]. The result of the subtraction is stored in a register, R[d].

Register-register Mode:

Assembler Syntax:

SUB d, s, t

Opcode:

00001

Format:
Type1 0.png
Operation:

d ← s - t
N ← d[15]
Z ← if (d == 0) 1; else 0
C ← (s[15] & t[15]) | (!d[15] & (s[15] | t[15]))
V ← (s[15] & t[15] & !d[15]) | (!s[15] & !t[15] & d[15])

LSL instruction

LSL

Mnemonic:

LSL

Description:

This instruction performs a logical bitwise shift on a register, R[d]. It shifts the value left by a 5 bit immediate value. The result of this operation is stored in the register, R[d].

Register-immediate Mode:

Assembler Syntax:

LSL d, simm5

Opcode:

01001

Format:
Type3.png
Operation:

d ← d << simm5
N ← d[15]
Z ← if (d == 0) 1; else 0
C ← 0
V ← 0


LSR instruction

LSR

Mnemonic:

LSR

Description:

This instruction performs a logical bitwise shift on a register, R[d]. It shifts the value right by a 5 bit immediate value. The result of this operation is stored in the register, R[d].

Register-immediate Mode:

Assembler Syntax:

LSR d, simm5

Opcode:

01000

Format:
Type3.png
Operation:

d ← d >> simm5
N ← d[15]
Z ← if (d == 0) 1; else 0
C ← 0
V ← 0


AND instruction

AND

Mnemonic:

AND

Description:

This instruction performs a logical bitwise AND between a register, R[s], and another register (R[t]) or 16 bit immesdiate value. The result of this operation is stored in the register, R[d].

Register-register Mode:

Assembler Syntax:

AND d, s, t

Opcode:

00111

Format:
Type1 0.png
Operation:

d ← s & t
N ← d[15]
Z ← if (d == 0) 1; else 0
C ← 0
V ← 0



Register-long immediate Mode:

Assembler Syntax:

AND d, s, simm16

Opcode:

00111

Format:
Type1 2.png
Operation:

d ← s & simm16
N ← d[15]
Z ← if (d == 0) 1; else 0
C ← 0
V ← 0

NOT instruction

NOT

Mnemonic:

NOT

Description:

This instruction performs a logical bitwise NOT on a register, R[s]. The result of this operation is stored in the register, R[d].

Register-register Mode:

Assembler Syntax:

NOT d, s

Opcode:

00000

Format:
Type1 0.png
Operation:

d ← !s
N ← d[15]
Z ← if (d == 0) 1; else 0
C ← 0
V ← 0


OR instruction

OR

Mnemonic:

OR

Description:

This instruction performs a logical bitwise OR between a register, R[s], and another register (R[t]) or 16 bit immesdiate value. The result of this operation is stored in the register, R[d].

Register-register Mode:

Assembler Syntax:

OR d, s, t

Opcode:

00110

Format:
Type1 0.png
Operation:

d ← s | t
N ← d[15]
Z ← if (d == 0) 1; else 0
C ← 0
V ← 0



Register-long immediate Mode:

Assembler Syntax:

OR d, s, simm16

Opcode:

00110

Format:
Type1 2.png
Operation:

d ← s | simm16
N ← d[15]
Z ← if (d == 0) 1; else 0
C ← 0
V ← 0


XOR instruction

XOR

Mnemonic:

XOR

Description:

This instruction performs a logical bitwise XOR between a register, R[s], and another register (R[t]) or 16 bit immesdiate value. The result of this operation is stored in the register, R[d].

Register-register Mode:

Assembler Syntax:

XOR d, s, t

Opcode:

00100

Format:
Type1 0.png
Operation:

d ← s ^ t
N ← d[15]
Z ← if (d == 0) 1; else 0
C ← 0
V ← 0



Register-long immediate Mode:

Assembler Syntax:

XOR d, s, simm16

Opcode:

00100

Format:
Type1 2.png
Operation:

d ← s ^ simm16
N ← d[15]
Z ← if (d == 0) 1; else 0
C ← 0
V ← 0


LOAD instruction

LOAD

Mnemonic:

LOAD

Description:

This instruction loads data from a location in memory in to a destination register, R[d]. The addressed memory location is determined by the addition of a register, R[s], to another register (R[t]) or an immediate value (either 5 or 16 bits).

Register-register Mode:

Assembler Syntax:

LOAD d, t(s)

Opcode:

00010

Format:
Type1 0.png
Operation:

d ← mem[s + t]


Register-immediate Mode:

Assembler Syntax:

LOAD d, simm5(s)

Opcode:

01110

Format:
Type2.png
Operation:

d ← mem[s + simm5]


Register-long immediate Mode:

Assembler Syntax:

LOAD d, simm16(s)

Opcode:

00010

Format:
Type1 1.png
Operation:

d ← mem[s + simm16]

STORE instruction

STORE

Mnemonic:

STORE

Description:

This instruction stores data from a register, R[d], in to a location in memory. The addressed memory location is determined by the addition of a register, R[s], to another register (R[t]) or an immediate value (either 5 or 16 bits).

Register-register Mode:

Assembler Syntax:

STORE d, t(s)

Opcode:

00011

Format:
Type1 0.png
Operation:

mem[s + t] ← d


Register-immediate Mode:

Assembler Syntax:

STORE d, simm5(s)

Opcode:

01111

Format:
Type2.png
Operation:

mem[s + simm5] ← d


Register-long immediate Mode:

Assembler Syntax:

STORE d, simm16(s)

Opcode:

00011

Format:
Type1 1.png
Operation:

mem[s + simm16] ← d

PUSH instruction

PUSH

Mnemonic:

PUSH

Description:

This instruction will take a value from R[s] and store it at the top of the stack.

Register-register Mode:

Assembler Syntax:

PUSH s

Opcode:

01011

Format:
Type7 push.png
Operation:

sp ← sp - 1;
mem[sp] ← s

POP instruction

POP

Mnemonic:

POP

Description:

This instruction will take a value from the top of the stack and store it in R[d].

Register-register Mode:

Assembler Syntax:

POP d

Opcode:

01010

Format:
Type7 pop.png
Operation:

d ← mem[sp];
sp ← sp + 1

CALL instruction

CALL

Mnemonic:

CALL

Description:

This instruction will call a subroutine and store the return address on the stack.

Register-register Mode:

Assembler Syntax:

CALL s

Opcode:

10001

Format:
Type6 0.png
Operation:

sp ← sp - 1;
mem[sp] ← pc;
pc ← s

Register-immediate Mode:

Assembler Syntax:

CALL simm11

Opcode:

10011

Format:
Type4.png
Operation:

sp ← sp - 1;
mem[sp] ← pc;
pc ← pc + simm11

Register-immediate Mode:

Assembler Syntax:

CALL imm16

Opcode:

10001

Format:
Type6 1.png
Operation:

sp ← sp - 1;
mem[sp] ← pc;
pc ← imm16

RETURN instruction

RETURN

Mnemonic:

RETURN

Description:

This instruction will return from a subroutine. The instruction will restore the program counter and return the stack pointer to its value before the subroutine call.

Register-register Mode:

Assembler Syntax:

RETURN

Opcode:

10100

Format:
Type5.png
Operation:

pc ← mem[sp];
sp ← sp + 1

RETI instruction

RETI

Mnemonic:

RETI

Description:

This instruction will return from a subroutine. The instruction will restore the program counter and return the stack pointer to its value before the subroutine call.

Register-register Mode:

Assembler Syntax:

RETI

Opcode:

10101

Format:
Type5.png
Operation:

flags ← mem[sp];
sp ← sp + 1;
pc ← mem[sp];
sp ← sp + 1

SFA instruction

SFA

Mnemonic:

SFA

Description:

This instruction is a 'no operation'. It effectively does nothing at all.

Register-register Mode:

Assembler Syntax:

SFA

Opcode:

10110

Format:
Type5.png
Operation:

n/a

STI instruction

STI

Mnemonic:

STI

Description:

This instruction will set or clear the IE (interrupt enable) flag which will enable or disable interrupts.

Register-immediate Mode:

Assembler Syntax:

STI a

Opcode:

10010

Format:
Type8.png
Operation:

IE ← a; a ∈ {0, 1}

JUMPR instruction

JUMPR

Mnemonic:

JUMPR

Description:

This instruction will perform an unconditional relative jump, the jump target is the sum of the program counter and an 11-bit signed immediate.

Register-immediate Mode:

Assembler Syntax:

JUMPR simm11

Opcode:

11100

Format:
Type4.png
Operation:

pc ← pc + 1;
pc ← pc + simm11

JUMPA instruction

JUMPA

Mnemonic:

JUMPA

Description:

This instruction will perform an unconditional absolute jump, the jump target is either a 16-bit immediate or the contents of R[s].

Register-register Mode:

Assembler Syntax:

JUMPA s

Opcode:

10000

Format:
Type6 0.png
Operation:

pc ← s

Register-long immediate Mode:

Assembler Syntax:

JUMPA imm16

Opcode:

10000

Format:
Type6 1.png
Operation:

pc ← imm16

JUMPV instruction

JUMPV

Mnemonic:

JUMPV

Description:

This instruction will perform a relative jump if the V (Overflow) flag is set, the jump target is the sum of the program counter and an 11-bit signed immediate.

Register-immediate Mode:

Assembler Syntax:

JUMPV simm11

Opcode:

11000

Format:
Type4.png
Operation:

pc ← pc + 1;
if (V) pc ← pc + simm11

JUMPC instruction

JUMPC

Mnemonic:

JUMPC

Description:

This instruction will perform a relative jump if the C (Carry) flag is set, the jump target is the sum of the program counter and an 11-bit signed immediate.

Register-immediate Mode:

Assembler Syntax:

JUMPC simm11

Opcode:

11001

Format:
Type4.png
Operation:

pc ← pc + 1;
if (C) pc ← pc + simm11

JUMPnC instruction

JUMPnC

Mnemonic:

JUMPnC

Description:

This instruction will perform a relative jump if the C (Carry) flag is not set, the jump target is the sum of the program counter and an 11-bit signed immediate.

Register-immediate Mode:

Assembler Syntax:

JUMPnC simm11

Opcode:

11101

Format:
Type4.png
Operation:

pc ← pc + 1;
if (!C) pc ← pc + simm11

JUMPN instruction

JUMPN

Mnemonic:

JUMPN

Description:

This instruction will perform a relative jump if the N (Negative) flag is set, the jump target is the sum of the program counter and an 11-bit signed immediate.

Register-immediate Mode:

Assembler Syntax:

JUMPN simm11

Opcode:

11011

Format:
Type4.png
Operation:

pc ← pc + 1;
if (N) pc ← pc + simm11

JUMPnN instruction

JUMPnN

Mnemonic:

JUMPnN

Description:

This instruction will perform a relative jump if the N (Negative) flag is not set, the jump target is the sum of the program counter and an 11-bit signed immediate.

Register-immediate Mode:

Assembler Syntax:

JUMPnN simm11

Opcode:

11111

Format:
Type4.png
Operation:

pc ← pc + 1;
if (!N) pc ← pc + simm11

JUMPZ instruction

JUMPZ

Mnemonic:

JUMPZ

Description:

This instruction will perform a relative jump if the Z (Zero) flag is set, the jump target is the sum of the program counter and an 11-bit signed immediate.

Register-immediate Mode:

Assembler Syntax:

JUMPZ simm11

Opcode:

11010

Format:
Type4.png
Operation:

pc ← pc + 1;
if (Z) pc ← pc + simm11

JUMPnZ instruction

JUMPnZ

Mnemonic:

JUMPnZ

Description:

This instruction will perform a relative jump if the Z (Zero) flag is not set, the jump target is the sum of the program counter and an 11-bit signed immediate.

Register-immediate Mode:

Assembler Syntax:

JUMPnZ simm11

Opcode:

11110

Format:
Type4.png
Operation:

pc ← pc + 1;
if (!Z) pc ← pc + simm11